The invention relates to a method of fabricating a landing plug of a semiconductor device, and more specifically, to a method of fabricating a landing plug of a semiconductor device which includes performing a double patterning process to obtain a device having a half pitch of 30 nm.
In forming semiconductor devices, it is difficult to form line/space patterns of 50 nm or less in size in a single exposure using 1.0 (or less) numerical aperture (NA) ArF exposure equipment, even when employing an immersion lithography process. To improve resolution in lithography processes and increase process margins, diversified research on double patterning has been performed. Double patterning is a process wherein a wafer coated with a photoresist material is exposed using two masks, and then developed. Double patterning is used primarily for complicated patterns (i.e., not simple lines or contacts), or for exposure of dense patterns and isolated patterns to increase process margins. The double patterning process involves exposing and etching a first pattern having a spacing that is twice the desired spacing, and then exposing and etching a second pattern having the same pattern spacing between the first pattern. Because the second mask and etching processes are performed after the first mask and etching processes, a degree of overlay can be measured. In relation to this misalignment and other factors, defects may be overcome and desired resolutions can be obtained. However, this technique increases the number of process steps, thereby complicating semiconductor assembly and increasing production costs.
The double patterning process can be performed in a negative tone or in a positive tone. Negative tone double patterning is a method for obtaining a desired pattern by forming a pattern in the first mask process and removing the same pattern in the second mask process. Positive tone double patterning is a method for obtaining a desired pattern by adding a pattern from the first mask process to a pattern from the second mask process.
In prior art processes of manufacturing semiconductor devices, a device having a half pitch of 30 nm has been developed, but it is difficult to perform patterning in devices with such a small half pitch. In order to form a pattern having such a small pitch, the numerical aperture (NA) of exposure equipment is necessarily high and resolution accordingly decreases. Therefore, technical solutions related to both equipment and photoresists are under consideration. Specifically, a double exposure process for exposing a pattern twice is frequently used.
In a conventional landing plug contact forming process, an I-type landing plug contact mask has been used. However, the I-type mask does not completely cover a double-lined word line (gate) and a space of both sides. Thus, it is difficult to form a desired pattern.